Field effect transistor with local source/drain insulation and associated method of production

ABSTRACT

A field-effect transistor (FET) with local source-drain insulation is described. The FET includes a semiconductor substrate, source and drain depressions, a depression insulation layer, an electrically conductive filling layer, a gate dielectric, and a gate layer. The depression insulation layer is formed at least in bottom regions of the source and drain depressions. The electrically conductive filling layer realizes source and drain regions and fills the source and drain depressions at a surface of the depression insulation layer. The gate dielectric is formed at a substrate surface between the source and drain depressions. The gate layer (is formed at a surface of the gate dielectric. The source and drain depressions have, in an upper region, a widening with a predetermined death for realizing defined channel connection regions.

This application is the national stage application of internationalapplication number PCT/DE03/003130, filed on Sept. 19, 2003, whichclaims the benefit of priority to German Patent Application 102 46718.8, filed on Oct. 7, 2002, herein incorporated herein by reference.

The present invention relates to a field-effect transistor with localsource/drain insulation and to an associated fabrication method and, inparticular, to a field-effect transistor with structures in the sub-100nm range, which can be used in so-called mixed-signal circuits.

The electrical properties of field-effect transistors are influenced bya multiplicity of parameters, so-called junction capacitances, inparticular, bringing about undesirable parasitic effects in thefield-effect transistor. Such junction capacitances are caused inparticular at the pn junctions of the source and drain regions in thesemiconductor substrate since relatively high parasitic capacitancesarise at this location on account of space charge or depletion zones.

In order to avoid or decrease such junction capacitances, so-called SOIsubstrates (silicon on insulator) have conventionally been used, wherebyat least a lower region of respective source and drain regions has beendirectly bounded by the insulation region of the SOI substrate or wafer.What are disadvantageous about such semiconductor circuits in an SOIsubstrate, however, are the significantly increased costs and also theassociated disadvantages in so-called mixed-signal circuits. While afully depleted channel region is often even desirable in short-channelfield-effect transistors, field-effect transistors with long channelregions require a connection possibility in order to prevent theseregions from being charged and in order to realize the highest possiblelinearity of the characteristic curves. In the same way, a connectionpossibility for the channel region is also of importance for theso-called matching behavior of the transistors, in order, by way ofexample, to enable an identical behavior of two identical transistors ina semiconductor circuit. Therefore, for mixed-signal circuits, inparticular, the use of SOI substrates yields only inadequate results.Furthermore, SOI substrates have only a poor thermal linking of theactive regions.

The document JP 021 280 430 A discloses a method for fabricating afield-effect transistor, in which case, for producing local source/draininsulations, an oxygen implantation is carried out in such a way thatoxygen ions are implanted directly below the source and drain regions inthe semiconductor substrate and are subsequently converted into a buriedsilicon dioxide layer. What are disadvantageous in this case, however,are the relatively inaccurate formation of these buried insulationregions, such as, for example, an unsharp lateral transition betweenimplanted and non-implanted region, and, in particular, a lack ofapplicability of such methods to field-effect transistors withstructures in the sub-100 nm range.

Therefore, the invention is based on the object of providing afield-effect transistor with local source/drain insulation and anassociated fabrication method, it being possible to reduce junctioncapacitances in a particularly simple manner.

In particular through the use of a source depression and a draindepression, which have a depression insulation layer at least in abottom region, and an electrically conductive filling layer, which isformed for realizing source and drain regions and for filling thedepressions at the surface of the depression insulation layer, afield-effect transistor with reduced junction capacitances is obtainedwhich can be realized simply and cost-effectively both for mixed-signalcircuits and for feature sizes of less than 100 nm.

Besides the depression bottom insulation layer, the depressioninsulation layer may also have a depression sidewall insulation layer,which, however, does not touch the gate dielectric, thus resulting infurther reduced junction capacitances and shallow or accurately definedextension or connection regions for the channel region.

In order to realize highly accurately defined channel connectionregions, the source and drain depressions may have a predetermined widthin the upper region with a predetermined depth. In this way, the desiredshallow connection regions for the channel regions can be realized veryprecisely and the very shallow implantations that are usually employed,the problems due to diffusion-promoting effects of defects and also veryshort RTP annealing steps (rapid thermal process) with their poorreproducibility or a pre-amorphization and defect implantations areobviated. However, on account of the depression sidewall insulationlayers, it is possible to significantly reduce the high leakage currentsand junction capacitances that usually occur in this region.

In order to improve a deposition process in the source and draindepressions, the electrically conductive filling layer may have a seedlayer, as a result of which even very narrow and deep source and draindepressions or holes can be filled sufficiently well.

Furthermore, the depression sidewall insulation layer may also extendinto a region below the gate dielectric or below the channel region.What can thereby be achieved is that short-channel transistors areinsulated from the substrate and long-channel transistors on the samewafer acquire a possibility of connection to the substrate. Thus, theoptimal devices are produced both for digital circuits and formixed-signal circuits. This is particularly advantageous for an SoC(system on chip) integration.

The invention is described in more detail below using exemplaryembodiments with reference to the drawing.

In the figures:

FIG. 1 shows a simplified sectional view of a field-effect transistorwith local source/drain insulation in accordance with a first exemplaryembodiment;

FIG. 2 shows a simplified sectional view of a field-effect transistorwith local source/drain insulation in accordance with a second exemplaryembodiment;

FIGS. 3A to 3I show simplified sectional views for illustratingessential method steps in the fabrication of a field-effect transistorwith local source/drain insulation in accordance with a third exemplaryembodiment;

FIG. 4 shows a partly enlarged sectional view of a field-effecttransistor in accordance with the third exemplary embodiment; and

FIGS. 5A and 5B show simplified sectional views for illustratingessential method steps in the fabrication of a field-effect transistorwith local source/drain insulation in accordance with a fourth exemplaryembodiment.

FIG. 1 shows a simplified sectional view of a field-effect transistorwith local source/drain insulation in accordance with a first exemplaryembodiment, in which case, in a semiconductor substrate 1, which ispreferably composed of a silicon semiconductor material, active regionsare formed by means of an STI method (shallow trench isolation) forforming shallow trench isolations 2. Said shallow trench isolations 2may be embodied for example in strip form in the semiconductor substrate1, thus resulting in strip-type active regions situated in between.

In this case, the field-effect transistor has a gate stack G formed atthe surface of the semiconductor substrate 1, which gate stackessentially has a gate dielectric such as e.g. a gate oxide layer 3 andalso an actual gate or control layer 4. At the sides of the gate stackG, a source depression SV and a drain depression DV are then formed in amanner spaced apart from one another in the semiconductor substrate 1, aregion which lies below the gate dielectric 3 representing a channelregion. In this case, the depressions formed may be cutouts, holes,trenches, etc. with a corresponding depth in the semiconductor substrate1.

In accordance with FIG. 1, a depression insulation layer VI is in eachcase formed in a bottom region of the source depression SV and of thedrain depression DV, which layer represents a local source and draininsulation with respect to the semiconductor substrate 1 and thussignificantly reduces a junction capacitance of a respective source anddrain region. In contrast to conventional depression insulation layersformed by means of oxygen implantations, the local source and draininsulations according to the invention are formed in narrowly delimitedfashion and very exactly in the depression. Furthermore, thefield-effect transistor has an electrically conductive filling layer Ffor realizing the actual source and drain regions S and D, the fillinglayer F being formed at the surface of the depression insulation layerand filling the source and drain depressions SV and DV.

This results in a field-effect transistor with local source and draininsulation which has a significantly reduced junction capacitance at itssource and drain regions S and D and furthermore enables a connectionpossibility for the channel region lying between the source and drainregions. In this way, field-effect transistors with long channels andhigh linearity and also outstanding matching properties can also berealized in particular in mixed-signal circuits. Furthermore, such alocal source and drain insulation also results in a thermal linking ofthe channel regions to the semiconductor substrate 1 which is greatlyimproved in comparison with SOI substrates. Particularly in the case offield-effect transistors with lateral structures in the sub-100 nm rangeor <100 nm, it is thus possible to fabricate field-effect transistorswith further improved electrical properties in a relatively simplemanner. Depending on a respective type of fabrication of the depressioninsulation layer VI and respective dimensions of the field-effecttransistor, the source and drain depressions may have a depth ofapproximately 50 to 300 nm. In this case, the electrical properties ofthe field-effect transistor can be set very accurately particularly inthe case of perpendicular sidewalls of the depressions SV and DV.

Silicon dioxide, for example, is used as the gate dielectric, but otherdielectric layers can also be used. Amorphous silicon or polysilicon ispreferably used as the gate layer 4, but metal gates or other materialscan also be used. In particular, for the gate stack G, it is alsopossible to realize other layer structures as are known for example fromthe field of nonvolatile memory elements (flash EPROM, E²PROM, etc.).

FIG. 2 shows a simplified sectional view of a field-effect transistorwith local source/drain insulation in accordance with a second exemplaryembodiment, identical reference symbols designating elements or layersidentical or corresponding to those in FIG. 1 and a repeated descriptionbeing dispensed with below.

In the exemplary embodiment in accordance with FIG. 2, the depressioninsulation layer VI has not only a depression bottom insulation layerformed in the bottom region of the source and drain depressions SV andDV, but moreover a depression sidewall insulation layer, which, however,does not touch the gate dielectric 3 and thus enables a defined channelconnection region KA for the connection of a channel region lying belowthe gate dielectric 3. This results in channel connection regions KAwhich have very low leakage currents and further reduced junctioncapacitances. It is thus possible to avoid the methods usually used forforming such shallow connection regions by means of shallowimplantations, pre-amorphization or defect implantations and also shortRTP annealing steps (rapid thermal process). The fact that thedimensions of the source and drain depressions can be set veryaccurately means that the electrical properties of the field-effecttransistors formed therewith can also be defined very accurately, thusresulting in semiconductor components with significantly reducedjunction capacitances.

When polysilicon is used as the filling layer F, the extension orconnection regions KA may be realized by means of outdiffusion, therebyproducing dopant profiles with a maximum gradient.

FIGS. 3A to 3I show simplified sectional views for illustratingessential method steps in the fabrication of a field-effect transistorwith local source/drain insulation, once again identical referencesymbols designating layers or elements identical or similar to those inFIGS. 1 and 2 and a repeated description being dispensed with below.

In accordance with FIG. 3A, firstly in a preparatory method, a gatestack with a gate layer 4 and a gate dielectric 3 is formed on asemiconductor substrate 1. In the case of such a method, usuallyreferred to as a gate process, firstly a pad oxide (not illustrated) isdeposited at the surface of the semiconductor substrate 1 and a padnitride (not illustrated) is subsequently formed at the surface of thepad oxide. Afterward, a shallow trench isolation 2 is formed in thesemiconductor substrate 1 by means of a conventional STI method (shallowtrench isolation) and then at least the pad nitride layer is removedagain. One or more implantations are subsequently effected for formingwell and/or channel doping regions in the semiconductor substrate 1, italso being possible to realize a multiple well construction depending onthe semiconductor circuit to be formed. Afterward, preferably a thermaloxidation of the substrate surface SO is effected in order to form thegate dielectric 3, as a result of which e.g. a high-quality gate oxideis formed. Afterward, by way of example, a deposition of polysiliconwith a thickness of 100 nm, for example, is effected in order to formthe gate layer 4 and, by way of example, a TEOS insulation layer with athickness of approximately 50 nm is deposited at the surface thereof inorder to form a hard mask layer 5. Afterward, for the patterning of atleast the gate layer 4, a photolithographic method is firstly applied tothe hard mask layer 5, the gate layer 4 subsequently being patternedusing the patterned hard mask layer 5, preferably by means of ananisotropic etching method (RIE, reactive ion etching). Finally, afurther thermal oxidation or oxide deposition may be carried out forforming a gate sidewall insulation layer 6 at the sidewalls of the gatelayer 4, as a result of which a protection layer having a thickness ofapproximately 6 nm is obtained. In this case, the gate sidewallinsulation layer 6 serves as an etching stop layer for later etchingsteps and also as a lateral protection layer for the relativelysensitive gate dielectric 3.

The sectional view illustrated in FIG. 3A is obtained in this way, italso being possible to carry out alternative methods for forming andpatterning a gate stack with a gate layer 4 and a gate dielectric 3 on asemiconductor substrate 1.

Afterward, source and drain depressions are formed in the semiconductorsubstrate 1 at the gate stack.

In accordance with FIG. 3B, it is possible, by way of example, firstlyto form first depressions V1 for realizing channel connection regions KAin the semiconductor substrate 1, a cutout having a depth of d1=10 to 50nm being formed preferably by means of an anisotropic etching methodsuch as e.g. RIE (reactive ion etching) or alternatively by wet-chemicalmeans. In this case, the depth of this first depression V1 serves as anoptimization parameter for the fabrication of the extension or channelconnection region.

At this point in time it is possible, optionally, to form a first thinsemiconductor protection layer (not illustrated) at least in the regionof the channel connection region KA and preferably over the whole area,in order to protect the semiconductor surface (silicon) from asubsequent nitride deposition, which is generally problematic forsilicon semiconductor materials. Accordingly, this first semiconductorprotection layer preferably comprises a silicon oxide layer.

Afterward, in accordance with FIG. 3B, spacers 7 are formed at the gatestack, the gate stack essentially being composed of the gate dielectric3, the gate layer 4, the hard mask layer 5 and the gate sidewallinsulation layer 6 (possibly present). The spacers 7 are preferablyformed by conformal, i.e. uniformly thick, deposition of silicon nitrideon the available surface and subsequent anisotropic etching-back, anLPCVD method (low pressure chemical vapor deposition), for example,being used for the deposition. Once again, the thickness of the spacers7 is also an optimization parameter for the channel connection regionKA, preferably spacer thicknesses of approximately 10 to 30 nm yieldingparticularly favorable connection properties.

The first depressions V1 are preferably formed using the gate stack andthe shallow trench isolation 2 as a mask, thus essentially resulting inself-aligning methods for a first depression V1.

In accordance with FIG. 3C, second depressions V2 are then formed withinthe first depressions V1 in the semiconductor substrate 1 using thespacers 7 formed at the gate stack and also the further spacers 7Aformed at the shallow trench isolation 2 as a mask. More precisely, asecond depression V2 having a depth d2 of approximately 40 to 250 nm isformed by means of a silicon RIE method, for example, thus yielding atotal depth for the source and drain depressions SV and DV ofd1+d2=approximately 50 to 300 nm, measured from the substrate surfaceSO.

Finally, in order to form a depression insulation layer at least in abottom region of the source and drain depressions SV and DV, firstly aninsulation mask layer 8 is formed. In this case, the exposedsemiconductor material or silicon is preferably nitrided with NH₃ withina temperature range of 600 to 900° C. As an alternative, however, it isalso possible to carry out a nitride deposition for realizing theinsulation mask layer 8. The silicon nitride thickness sought, orthickness of the insulation mask layer 8, is approximately 1 to 5 nm,for example. In principle, an additional thin oxide buffer layer (notillustrated) may again be produced below the deposited nitride for theprotection of the semiconductor material.

In accordance with FIG. 3D, in a subsequent step, the insulation masklayer 8 is removed at least in the bottom region of the source and draindepressions SV and DV, preferably an anisotropic etching method and inparticular an RIE nitride etching method being carried out foruncovering the bottom regions. In the case of a whole-area deposition ofthe insulation mask layer 8, only the horizontal areas are uncovered inthis case. Afterward, a depression bottom insulation layer 9 is formedin each case in the uncovered bottom regions of the source and draindepressions SV and DV, a thermal oxidation, for example, being carriedout on the uncovered semiconductor material. This results in theformation of, by way of example, a silicon oxide layer with a thicknessof 20 to 40 nm in the bottom region of the source and drain depressions.

As an alternative to thermal oxidation, it is also possible to carry outa so-called SELOX method (selective oxide deposition process) for theselective deposition of an insulating layer only in the bottom region ofthe source and drain depressions SV and DV. Accordingly, the depths forthe source and drain depressions are to be chosen depending on afabrication method respectively selected for the depression bottominsulation layer 9. With regard to the further technical details of theSELOX method, in particular, reference is made in particular to theliterature reference N. Elbel, et al., “A new STI-process based onselective oxide deposition” at Symposium on VLSI-Technology 1998.

Accordingly, the insulation mask layer 8 not only allows the horizontaland vertical areas to be oxidized separately, but furthermore reducesthe mechanical stress in the channel region.

In accordance with FIG. 3E, furthermore, it is optionally possible alsoto remove the remaining insulation mask layer 8 at the sidewalls of thesource and drain depressions SV and DV and to form depression sidewallinsulation layers 8A in the uncovered sidewall regions of thedepressions. More precisely, in order to remove the thin nitride layer 8at the sidewalls, a brief etching step is carried out and then a thermaloxidation at a temperature of approximately 800° C. or a wet oxidationis carried out in order to fabricate a depression sidewall insulationlayer 8A having a thickness of approximately 5 to 20 nm. The depressionbottom insulation layer 9 and also the depression sidewall insulationlayer 8A are preferably formed as silicon dioxide layers.

Afterward, the at least partially insulated source and drain depressionsSV and DV are then filled with a filling layer, preferably firstly aseed layer 10 being formed for realizing a later selective deposition ofpolysilicon. By way of example, a thin doped or undoped amorphous orpolycrystalline semiconductor layer is deposited, silicon or SiGepreferably being used, although alternative materials may also be usedas the seed layer 10. Afterward, in order to form a seed protectionlayer 11, the seed layer 10 is briefly oxidized or nitrided and,finally, a seed mask layer 12 is formed, a resist deposition preferablybeing carried out over the whole area. The sectional view illustrated inFIG. 3E is obtained after the seed mask layer 12 has been planarized bymeans of, by way of example, a chemical mechanical polishing method(CMP) using the seed protection layer 11 as a stop layer.

In accordance with FIG. 3F, the seed mask layer 12 is subsequentlycaused to recede right into the source and drain depressions SV and DV,a resist etching being carried out after a predetermined time, by way ofexample. Such a receding process can be carried out relativelyaccurately since the height of the gate stack is usually known veryaccurately. Using the seed mask layer 12 that has been caused to recederight into the source and drain depressions, the seed protection layer11 is then partially removed, i.e. the oxide and/or nitride layer areremoved except for the region covered by the seed mask layer 12. Theseed mask layer 12 that was caused to recede is subsequently removed,resist stripping preferably being carried out.

In accordance with FIG. 3G, afterward, the seed layer 10 is thenpartially removed using the seed protection layer 11 remaining in thesource and drain depressions SV and DV as a mask, a wet-chemical siliconetching method being carried out, by way of example. Finally, theresidual seed protection layer 11 is also completely removed. A nitrideand/or an oxide etching method is again carried out for removing theseed protection layer 11.

The amorphous or polycrystalline seed layer 10 remaining in the sourceand drain depressions SV and DV then allows a selective deposition or agrowth of semiconductor material on said layer, the rest of the regions,which are covered by oxide, remaining free of said growth layer 13.

In accordance with FIG. 3H, firstly the spacers 7 at the gate stack andalso the spacers 7A at the shallow trench isolation 2 are removed inorder to uncover the channel connection regions KA. This is preferablycarried out by means of a wet-chemical nitride etching.

It is optionally possible, in order to prevent grain formation during asubsequent growth process in the channel connection region, to form avery thin interface layer (not illustrated) made, for example, ofsilicon dioxide or silicon nitride. The growth layer 13 is subsequentlyformed on the seed layer 10 right into a region of the substrate surfaceSO, in particular doped or undoped amorphous or polycrystallinesemiconductor material being deposited selectively (with respect tosilicon dioxide) up to a thickness of approximately 50 to 400 nm. Inparticular, the various process conditions for the deposition ofamorphous or polycrystalline silicon on different substrates areutilized during this step. A so-called “raised source/drain” structureis thus produced.

In accordance with FIG. 3I, in a subsequent step, implantation spacers14 are formed at the sidewalls of the gate stack or the gate sidewallinsulation layer 6. Said implantation spacers 14 preferably againcomprise a silicon nitride layer. Afterward, the hard mask layer 5 canbe removed using an oxide etching, the trench isolations 2 and the TEOShard mask layer being caused to recede, but the gate sidewall insulationlayers 6 are protected by the implantation spacers 14. Finally, animplantation I of dopants is effected for doping the uncovered gatelayer 4 and also the growth layer 13 and, if appropriate, the seed layer10. This implantation is effected as usual by means of resist masktechnology, it being possible furthermore to carry out a thermalannealing step in order to activate the dopants.

The connections of source and drain are then effected by means ofoutdiffusion from these highly doped polysilicon layers, the dopedpolycrystalline or amorphous semiconductor material acting like aninfinite dopant source owing to the high diffusion constant along thegrain boundaries. The resulting advantages are very steep diffusionflanks and high dopings. Since the implantation I of the source anddrain regions S and D takes place directly into the amorphous orpolycrystalline semiconductor material, the underdiffusion of thechannel connection regions KA is not determined by implantation defectssince the latter recombine at the polysilicon grain boundaries. Owing tothis fact, it is possible to use larger temperature budgets in order toachieve better process control and higher activation of the dopants.

As an alternative to the deposition of undoped semiconductor material orsilicon, it is also possible to deposit in situ-doped semiconductormaterial. For this purpose, the wafer is covered with a mask layer andthe region for e.g. NFET transistors is then opened selectively. Dopedsemiconductor material is then deposited only in this region. Theprocess is repeated correspondingly for PFET transistors.

FIG. 4 shows a simplified partial sectional view for illustrating thechannel connection regions when using undoped or doped semiconductormaterial in accordance with the third exemplary embodiment describedabove.

FIGS. 5A and 5B show simplified sectional views of essential methodsteps in the fabrication of a field-effect transistor with localsource/drain insulation in accordance with a fourth exemplaryembodiment, identical reference symbols designating elements or layersidentical or corresponding to those in FIGS. 1 to 4 and a repeateddescription being dispensed with below.

In accordance with the present fourth exemplary embodiment, adescription is given of so-called field-effect transistors with “fullydepleted” channel regions. Field-effect transistors of this type aredesirable particularly when realizing fast short-channel transistors,since significantly increased speeds and clock frequencies can berealized as a result.

In this case, FIGS. 5A and 5B correspond to the method steps inaccordance with 3D and 3E, a depression sidewall insulation layer 8Awhich extends far into a region below the gate dielectric 3 being formedin order to realize the fully depleted channel regions. More precisely,a large thickness of the depression sidewall insulation layer 8A, lyingin a range of 20 to 30 nm, is produced for example by means of oxidationof the uncovered sidewalls of the source and drain depressions SV andDV. This high thickness produces a pinch-off of the so-called body orchannel region, thus resulting in a fully depleted structure in thechannel region.

The advantages of a field-effect transistor of this type, particularlywhen realizing circuits with transistors of different channel lengths,are that the transistors with a short channel length have the fullydepleted structures illustrated in FIG. 5B with their associated poweradvantages, as are also known from SOI semiconductor circuits, while thetransistors with a large channel length, as are also used formixed-signal circuits, furthermore exhibit the behavior of bulktransistors and, accordingly, in a customary manner, have a wellconnection for defining a potential in the channel region. Accordingly,it is possible in this way to fabricate quasi-SOI transistors andso-called bulk transistors simultaneously on one chip without usingadditional masks as it were in a self-aligning or automatic manner. Thismeans, in particular, an advantage for SoC circuits, where fast digitalcircuits and mixed-signal circuits are to be realized on one chip.

The invention as been described above on the basis of siliconsemiconductor circuits. However, it is not restricted thereto and alsoencompasses in the same way semiconductor circuits with alternativesemiconductor materials. In the same way, alternative materials can alsobe used in particular for the gate layer and the filling layer.

1. A field-effect transistor with local source-drain insulation, havinga semiconductor substrate; a source depression and a drain depression,which are formed in a manner spaced apart from one another in thesemiconductor substrate, wherein the source and drain depressions have,in an upper region, a widening with a predetermined depth for realizingdefined channel connection regions; a depression insulation layer, whichis formed at least in a bottom region of the source depression and ofthe drain depression, wherein the depression insulation layer has adepression sidewall insulation layer, which is formed in a sidewallregion of the source and drain depressions but does not touch the gatedielectric; and an electrically conductive filling layer, which isformed for realizing source and drain regions and for filling the sourceand drain depressions at a surface of the depression insulation layer,wherein the electrically conductive filling layer has a seed layer forimproving a deposition in the source and drain depressions, the seedlayer comprising silicon or SiGe; a gate dielectric, which is formed ata substrate surface between the source and drain depressions; and a gateelectrode layer, which is formed at a surface of the gate dielectric,wherein the depression sidewall insulation layer extends into a regionbelow the gate dielectric and overlaps with the gate electrode layer andthe gate dielectric.
 2. The field-effect transistor as claimed in claim1, wherein a gate insulation layer is formed at sidewalls of the gateelectrode layer.
 3. The field-effect transistor as claimed in claim 1,wherein the field-effect transistor is bounded by shallow trenchisolations.
 4. The field-effect transistor as claimed in claim 1,wherein the field-effect transistor has lateral structures <100 nm. 5.The field-effect transistor as claimed in claim 1, wherein the sourceand drain depressions have a depth of approximately 50 nm to 300 nm. 6.The field effect transistor as claimed in claim 1, wherein the sourceand drain depressions form a step at the widening.
 7. The field effecttransistor as claimed in claim 1, wherein the widening is filled with afirst material different from a second material of the seed layer.